1. Field of Invention
This invention relates to wiring structures and design structures in integrated circuits, and more particularly to wiring structures and design structures configured to reduce areas of high field density in integrated circuits.
2. Background of the Invention
Vertical natural capacitors are on-chip capacitors that are incorporated into the interconnect levels of integrated circuits, typically during Back-End-Of-The-Line (“BEOL”) processes. Such capacitors may be placed in close proximity to various components on the integrated circuit in order to minimize inductive or resistive losses that may occur when using off-chip capacitors. Vertical natural capacitors may be formed using the same processes that are used to form wiring on integrated circuits, using the native insulator material as the dielectric. Thus, these capacitors may be fabricated without additional mask layers or new films, making these capacitors relatively simple and inexpensive to produce.
Conventional vertical natural capacitors are typically formed as interleaved, comb-like structures in the interconnect levels of the integrated circuit. FIG. 1 shows one example of a conventional vertical natural capacitor 100. In this example, a first comb-like structure 102a, forming a first electrode, interleaves with a second comb-like structure 102b, forming a second electrode. Circles 104 represent potential locations for vias connecting the comb-like structures 102a, 102b to similar or identical structures immediately above or below, thereby forming a stack. FIG. 2 shows a side profile of the vertical natural capacitor 100 showing the stack of comb-like structures 102b and vias 200 interconnecting the structures 102b. 
One problem with the rectangular comb-like structures 102a, 102b of FIG. 1, as well as any other rectangular or x-y dimensioned wiring structure, is the corners, edges, or protrusions inherent in such structures. For example, FIG. 1 shows several corners 106 inherent in the comb-like structures 102a, 102b. These corners 106 may create areas of high electric field density which may cause capacitor breakdown, shorting, or current leakage through the dielectric. As will be explained in more detail in association with FIG. 6A, the rectangular configuration may also create areas of high field density when vias protrude from the sides of wires in such structures.
In view of the foregoing, what is needed is a curvilinear wiring structure that is able to reduce areas of high field density, thereby reducing capacitor and other wiring structure breakdown, shorting, and leakage through the dielectric. Ideally, such a wiring structure would be easily incorporated into the interconnect levels of an integrated circuit. Further needed is a conductive via having a cross-sectional shape substantially conforming to a curvilinear shape of a wiring structure, and thereby reduce areas of high field density caused by vias protruding from the sides of wires.